FIG. 1 is a cross-sectional view of a portion of a prior art insulated gate turn-off (IGTO) thyristor 10 described in the inventor's U.S. Pat. No. 9,806,152, incorporated herein by reference.
The IGTO thyristor 10 has an npnp layered structure that forms vertical npn and pnp transistors. The layered structure includes a p+ substrate 12, an n+ buffer layer 13, an n-layer 14 (pnp base), a p-well 36 (npn base), gate oxide 25 surrounding vertical gates 26 which are formed in the p-well 36, an intermediate p+ layer 37 formed in the p-well 36, an n-layer 38 over the p-well 36, and an n+ emitter 18. A metal cathode electrode 22 contacts the n+ emitter 18 through an opening in the dielectric layer 40. A metal anode electrode 20 contacts the p+ substrate 12.
FIG. 2 illustrates the relative impurity (dopant) concentrations along the vertical center-line of the IGTO thyristor 10.
When a forward voltage is applied between the cathode electrode 22 and anode electrode 20 and when the gates 26 are sufficiently biased positive, an n-type inversion layer surrounds the gates 26 in the p-well 36 and p+ layer 37, causing the effective p-type base of the npn transistor to be narrowed to increase its beta. Thus, the n+ emitter 18, the underlying n− layer 38, and the underlying p-well 36 form the source and body of a vertical n-channel MOSFET.
When the product of the betas of the npn and pnp transistors exceeds one, controlled latch-up of the thyristor is initiated by regenerative action. The p-well's highly doped intermediate p+ layer 37 allows better control of the npn transistor efficiency while also providing more independent control over the characteristics of the n− layer 14, the emitter-base junction characteristics, and the overall dopant concentration and thickness of the p-well 36 (npn base).
In the fabrication method described in U.S. Pat. No. 9,806,152, the p-well 36 initially extends to the top surface of the silicon. The intermediate p+ layer 37 is formed using a high energy deep implant after the p-well 36 is completely formed. The p-well 36 must be relatively thick in a high voltage IGTO thyristor, so the energy needed to implant the p+ layer 37 is much higher than the implant energies used for forming conventional low-power devices. Unfortunately, such high energy implanters are not present in most semiconductor manufacturing facilities. Additionally, deep implants cause damage to the crystalline structure, which reduces the carrier lifetimes.
The intermediate p+ layer 37 should have a p-dopant concentration at least 1.5 times higher than that of the remainder of the p-well 36. An upper limit to the p+ dopant concentration may be 10 times that of the p-well 36. A higher breakdown voltage of the device is achieved since the p+ layer 37 does not deplete as much as the more lightly doped p-well 36 (npn base) during an off state. So the dopant concentration of the p-well 36 can be reduced (compared with the prior art device) without lowering the breakdown voltage.
Additionally, electron injection efficiency from the n+ emitter 18 into the p-well 36 is improved due to the lower dopant concentration of the p-well 36.
Further, as a result the increased peak dopant level near the middle of the p-well 36 (a p base), the off-state beta of the npn transistor can be reduced, which further increases breakover voltage. Breakover is the voltage at which the thyristor conducts through the bulk silicon, rather than by gate-controlled action. Ideally, the breakover voltage is designed to be equal to the breakdown voltage of the inherent reverse biased pn junction.
When a threshold voltage is applied to the gate 26, the inversion of the p-well 36 and p+ layer 37 around the gate 26 effectively bypasses the p+ layer 37 by extending the npn transistor emitter to below the gate 26, so the p+ layer 37 only lowers the beta of the npn transistor when there is no inversion of the base.
After the high energy implant into the p-well 36, the n-layer 38 and n+ emitter 18 are formed by much lower energy ion implants of an n-type dopant into the top surface of the p-well 36 to convert the top surface to n-type.
Besides the difficulties of using a high energy implant to form the p+ layer 37, another issue with the fabrication technique described in U.S. Pat. No. 9,806,152 is that it is difficult to obtain an optimal dopant concentration in the n-layer 38 and the p-well 36, since the p-well 36 is counter-doped to form the n-layer 38 and n+ emitter 18. It is desirable to provide a relatively high dopant concentration in the p-well 36 to obtain a high breakdown voltage. So counter-doping the p-well 36 with relatively large doses of the n-type dopant to achieve the desired dopant concentration in the n-layer 38 and n+ emitter 18 is difficult. In other words, the dopant concentrations in the p-well and the n layer 38 are not independently controlled, which leads to trade-offs rather than optimization.
There are also trade-offs with forward voltage, switching losses, and breakdown voltage. So, it would be desirable to have independent control of the doping of the p-well 36, p+ layer 37, n-layer 38, and n+ emitter 18.
Another issue with the device of FIG. 1 is that the p+ layer 37 extends completely between the gates 26. So, the dopant concentration in the p+ layer 37 affects both the inversion layer during operation (e.g., affects the threshold voltage of the thyristor) and the p-channel MOSFET threshold voltage. This interdependency results in trade-offs in performance.
What is needed is a technique to form a structure similar to that of FIG. 1 that does not require a high energy implant to form the p+ layer 37 and does not suffer from the drawbacks discussed above.